1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of pillar transistors, and specifically relates to a pillar transistor layout.
2. Description of Related Art
FIGS. 1A and 1B are diagrams illustrating an example of a common semiconductor device: FIG. 1A is a diagram illustrating a logic circuit; and FIG. 1B is a specific circuit diagram.
Examples of semiconductor devices include one that includes two OR gates and one NAND gate as illustrated in FIG. 1A. As illustrated in FIG. 1B, such semiconductor device is provided using a plurality of transistors PM1 to PM4 and NM1 to NM4 connected to the same node.
In recent years, semiconductor devices that use pillar transistors and that include a plurality of transistors have been proposed (see, for example, JP2011-103339A). The pillar transistors enable the integration density of the semiconductor device to be enhanced by using silicon pillars that extend perpendicularly to the principal surface of the semiconductor substrate as channels; however, the area and/or characteristics may vary depending on the layout of the pillar transistors. In particular, in the case of circuit cells in which a plurality of transistors are used, in the same way that standard cells are used, a large difference may occur in chip size.
FIGS. 2A and 2B are diagrams for describing the configuration of a standard cell that employs pillar transistors: FIG. 2A is a diagram illustrating cell rows arranged in a peripheral circuit section next to array sections each including memory cells; and FIG. 2B is a diagram illustrating a configuration of a cell row in a standard cell.
As illustrated in FIG. 2A, in peripheral circuit section 200 of a semiconductor device, cell row 100 is arranged for each array section 300 including memory cells, and in cell row 100, cells each including transistors are arranged.
For example, in a semiconductor device including p-channel pillar transistors and n-channel pillar transistors, as illustrated in FIG. 2B, in each cell row, a p-channel pillar transistor formation region (transistor formation region in a well region in which n-type impurities have been diffused) in which p-channel pillar transistors are formed, and a n-channel pillar transistor formation region (transistor formation region in the well region in which p-type impurities have been diffused), power supply wiring regions and wiring regions for transistors in cells are provided.
Standard cells such as described above provide various combinational circuits by means of input/output wiring combinations. A standard cell enables the degree of freedom of combination to be enhanced by including a plurality of identical transistors, and also enables preventing variation in characteristics depending on the layout of the respective elements.
A layout of pillar transistors will be described below.
FIG. 3 is a circuit diagram illustrating an example of a semiconductor device.
The example illustrated in FIG. 3 includes four transistors M1 to M4, and a case where transistors M1 to M4 are provided using pillar transistors will be considered.
FIGS. 4A, 4B and 4C are diagrams illustrating an example of a structure of a cell where pillar transistors are included in the semiconductor devices illustrated in FIG. 3: FIG. 4A is a top view; FIG. 4B is a cross-sectional view along A-A′ indicated in FIG. 4A; and FIG. 4C is a cross-sectional view along B-B′ indicated in FIG. 4A.
Where pillar transistors are included in the semiconductor device illustrated in FIG. 3, as illustrated in FIGS. 4A, 4B and 4C, each of pillar transistors M1 to M4 is provided by arranging a plurality of unit pillar transistors 10. In each of unit pillar transistors 10, gate electrode 12 is formed on a side face of silicon pillar 11, which is a pillar section, formed in STI 50, via gate insulator film 13, and upper n-type diffusion layer 14 is formed on the upper portion of silicon pillar 11. Upper n-type diffusion layer 14 is connected to power supply wiring 30 on the surface via through-hole contact 20 formed in STI 50. Also, on the lower portion of silicon pillar 11, lower n-type diffusion layer 15 is formed and p-well 40 is also formed. Gate insulator film 13 and gate electrode 12 are jointly referred to as a sidewall gate electrode.
Each of pillar transistors M1 to M4 includes two pillar rows each including four unit pillar transistors 10 arranged therein. The distance between respective silicon pillars 11 is equal to or smaller than twice the film thickness of gate insulator film 13 and gate electrode 12, whereby gate electrodes 12 are embedded. The two pillar rows included in each of pillar transistors M1 to M4 are arranged in such a manner that a pillar row on the output side (or the power supply side) of a pillar transistor is sandwiched by pillar rows on the power supply side (or the output side) of pillar transistors, in order to avoid occurrence of differences among current paths as indicated by the dotted lines and the alternate long and short dash lines in the Figure, whereby no additional resistance occurs in the respective current paths. More specifically, adjacent to one pillar row of the two pillar rows included in pillar transistor M2, one pillar row of the two pillar rows included in pillar transistor M3 is arranged; adjacent to that pillar row, one pillar row of the two pillar rows included in pillar transistor M1 is arranged; adjacent to that pillar row, one pillar row of the two pillar rows included in pillar transistor M4 is arranged; adjacent to that pillar row, the other pillar row of the two pillar rows included in pillar transistor M2 is arranged; adjacent to that pillar row, the other pillar row of the two pillar rows included in pillar transistor M3 is arranged; adjacent to that pillar row, the other pillar row of the two pillar rows included in pillar transistor M1 is arranged; and adjacent to that pillar row, the other pillar row of the two pillar rows included in pillar transistor M4 is arranged. The distance between silicon pillars 11 of the respective pillar rows is larger than twice the film thickness of gate insulator film 13 and gate electrode 12.
In each of the two pillar rows included in each of pillar transistors M1 to M4, insulator pillar 61 for gate power supply is provided and connected to gate wiring 63 via contact plug 62, whereby pillar rows included in a same pillar transistor are connected to the corresponding one by gate lead wires 70a to 70d. 
Lower n-type diffusion layer 15 that are formed on the lower portions of silicon pillars 11 connect respective pillar rows that are adjacent to each other, and below the lower n-type diffusion layer 15, p-well 40 is formed so as to cover all of unit pillar transistors 10.
As described above, if a semiconductor device including pillar transistors arranged therein has an increased number of pillar rows, the area increases. In semiconductor devices, there is a demand for an increase in integration density, and thus, such area increase is not desirable. Furthermore, there is a problem in that a resistance of the lower diffusion layer increases along with the area increase.